Integrated circuits are formed by interconnecting a number of electronic devices formed on a semiconductor substrate. The electronic devices (such as transistors, resistors, capacitors, diodes, etc) are interconnected by forming metal lines in dielectric layers formed above the semiconductor substrate. Traditionally, the dielectric layers have been formed using silicon oxide deposited using a chemical vapor deposition (CVD) process. The interconnect structure introduces stray capacitance into the integrated circuit that reduces the speed at which the integrated circuit can operate. The stray capacitance is proportional to the dielectric constant of the dielectric layers and one method of reducing the stray capacitance is to use dielectric material with a low dielectric constant to form the IC interconnect structures.
Low dielectric constant (low k) dielectric material has a higher porosity compared to silicon oxide and will be more susceptible to process induced damage and impurity diffusion during the fabrication of the integrated circuit. During integrated circuit manufacture, the interconnect structures are typically formed by first forming a low k dielectric layer over the silicon substrate. A trench is then formed in the low k dielectric material using a photoresist mask and a chemical plasma etching process. A barrier layer is formed in the trench and copper is formed over the barrier layer to fill the trench. Chemical mechanical polishing is used to remove the excess copper leaving a copper metal line formed in the low k dielectric layer. During the chemical plasma etching process used to form the trench, the low k dielectric layer can be modified by exposure to the chemical plasma. The modification of the low k dielectric layer often takes the form of a replacement of a CH3 group in the low k dielectric with a silanol group resulting in an increase in the dielectric constant of the low k dielectric layer. In addition, during the formation of the barrier layer, the porosity of the low k dielectric layer often results in the unwanted diffusion of the metallic barrier layer into the low k dielectric layer. This is illustrated in FIG. 1.
As illustrated in FIG. 1, a dielectric layer 20 is formed over a semiconductor substrate 10. The semiconductor substrate 10 will contain electronic devices such as transistors that are omitted from the Figure for clarity. A dielectric layer is formed over the semiconductor substrate 10 and a copper interconnect metal line 40 is formed in a trench that is formed in the dielectric layer. As described above, a barrier layer 30 is formed in the trench prior to the formation of the copper metal line 40. Following the formation of the copper interconnect line 40, a second dielectric layer 50 is formed over the first dielectric layer 20. The second dielectric layer 50 is formed using a low k dielectric material. A trench and via are formed in the low k dielectric layer using a photoresist masks and chemical plasma etching processes. As described above, during the chemical plasma etch processes, the incorporation of a silanol group into the low k dielectric layer will result in an increase in the dielectric constant of the low k dielectric layer 50. During the formation of the barrier layer 60, portions of the barrier layer 80 will diffuse into the low k dielectric layer 50 resulting in increased leakage currents and/or integrated circuit failure. Following the formation of the barrier layer 60, copper is used to form the copper line and via structure 70 shown in FIG. 1.
There is therefore a great need for a method to reduce the silanol incorporation into the low k dielectric material and to inhibit the diffusion of the barrier layer material. The instant invention addresses this need.